1. Field of the Invention
This invention relates to an insulated gate field effect semiconductor device using a thin film semiconductor (hereinafter referred to as a TFT) and a method for forming the insulated gate field effect semiconductor device, and particularly to a gate electrode and a method for forming the gate electrode.
2. Description of Related Art
A self-alignment type of structure has been known as a conventional TFT structure. In this structure, impurity material which provides one conductivity type is doped by an ion implantation method or the like using a gate electrode portion as a mask to form source/drain regions.
FIGS. 1A and 1B show a representative structure of this self-alignment structure of a TFT. In FIG. 1A, the structure includes an insulating substrate 21 of glass or the like, a thin film semiconductor layer 22 in which a source region 25, a channel forming region 27 and a drain region 26 are formed, a gate insulating film 23 and a gate electrode 24. Also, electrodes, layer insulating films, wirings, etc. which are well known but are not shown in FIG. 1A, are also formed in this structure.
In FIG. 1A, the semiconductor layer 22 is formed of amorphous silicon or crystallized amorphous silicon. The source region 25 and the drain region 26 are doped with phosphorus to form N-type regions. Accordingly, the TFT as shown in FIG. 1A is an N-channel type TFT. The gate insulating film 23 is formed of silicon oxide (SiO.sub.2), and the gate electrode 24 is formed of a silicon film which is doped with a large amount of phosphorus in order to reduce the resistance of the gate electrode 24.
The TFT shown in FIG. 1A is formed as follows. The amorphous silicon semiconductor layer 22 is first formed on the substrate 21 by a vapor phase method. Thereafter, the amorphous silicon semiconductor layer 22 is heated or irradiated with a laser beam in order to crystallize it, whereby the amorphous silicon semiconductor layer is transformed to crystallized silicon.
Subsequently, an oxidized silicon film serving as the gate insulating film 23 is formed by a sputtering method or the like and a silicon film doped with phosphorus, serving as the gate electrode 24, is formed by a vapor phase method or the like. Thereafter the gate insulating film 23 and the gate electrode 24 are formed in a patterning process to obtain an intermediate product having the shape shown in FIG. 1A. Subsequently, implantation (introduction) of phosphorus ions (hereinafter referred to as "ion implantation") is performed using the gate electrode 24 as a mask to form the source region 25 and the drain region 26 in a self-alignment structure. In this case, the channel forming region 27 is automatically formed.
Thereafter, through heat treatment, activation of the introduced phosphorus impurity and scratch of the semiconductor layer 22 in the ion implantation process are annealed. In this heat treatment, the gate electrode 24 formed of amorphous silicon is crystallized.
In this case, the following problem occurs.
In the heat treatment after the ion implantation process, the phosphorus diffuses from the gate electrode 24 and penetrates through the gate insulating film 23 to the channel forming region 27, as indicated by arrows 28 of FIG. 1B, so that the channel forming region 27 becomes an N-type region. As a result, the channel forming region does not function effectively, and the characteristic of the TFT deteriorates.
In order to solve the above problem, the following methods (a) to (d) may be adopted:
(a) Adoption of a doping method which requires no heat treatment, PA0 (b) Lowering the heat treatment temperature and shortening the heat treatment time, PA0 (c) Lowering the concentration of introduced phosphorus ions into the gate electrode 24, and PA0 (d) Use of a metal material requiring no ion implantation for the gate electrode.
The method (a) is not realistic because the doping system itself must be altered. That is, those devices and forming methods which are presently used cannot be utilized.
The method (b) cannot obtain various effects, such as the improvement of interface characteristics at the interface between the channel forming region 27 and the gate insulating film 23 which are obtained by heat treatment, the restoration of damage of the semiconductor layer 22 which occurs in the ion implantation process, etc., and thus does not basically solve the problem. In practical use, as a compromise, a heat treatment condition is set in a suitable permissible range in consideration of the treatment temperature and treatment time in the heat treatment process and the degree of diffusion of the impurities into the channel forming region.
The method (c) necessarily causes the resistance of the gate electrode to be increased, and this causes an increase in wiring resistance and cannot obtain the characteristics of the TFT.
In the method (d), the heat tolerance temperature of the metal material of the gate electrode 24 is an important factor in the heat treatment process after ion implantation and a subsequent protection film forming process. Therefore, the heat treatment temperature is restricted. Further, there is a problem in that although the gate electrode is not melted, the metal material of the gate electrode 24 diffuses into the channel forming region 27.
The above problems occur similarly for both N-channel type Tats and P-channel type TFTS, and are not dependent on elements introduced by ion implantation.